Hybrid power rail structure

ABSTRACT

An integrated circuit structure includes a substrate having a front side and a back side, the back side being an opposite side of the substrate from the front side. A first power rail extends in a first direction, is embedded in the front side of the substrate, and provides a first supply voltage. A second power rail provides a second supply voltage different from the first supply voltage, extends in the first direction, is embedded in the front side of the substrate, and is separated from the first power rail in a second direction different from the first direction. A first device is positioned between the first power rail and the second power rail and located on the front side of the substrate. A first via structure extends to the back side of the substrate and is electrically coupled to the second power rail.

PRIORITY CLAIM AND CROSS-REFERENCE

This application claims priority to U.S. Provisional Patent ApplicationSer. No. 62/738,673 filed Sep. 28, 2018, which is incorporated herein byreference in its entirety.

BACKGROUND

Cells are elements for designing and building integrated circuits (IC).The cells are configured to form functional circuits. Typically, powerrails are laid out on the boundaries of the cells to provide power forthe cells to operate. As chip sizes get smaller, more efficient powerrail structures are used to provide power to the cells.

BRIEF DESCRIPTION OF THE DRAWINGS

Aspects of the present disclosure are best understood from the followingdetailed description when read with the accompanying figures. It isnoted that, in accordance with the standard practice in the industry,various features are not drawn to scale. In fact, the dimensions of thevarious features may be arbitrarily increased or reduced for clarity ofdiscussion.

FIG. 1 is a block diagram of an IC having a semiconductor device, inaccordance with some embodiments.

FIGS. 2A-2D are multiple views of an IC with a hybrid power rail (HPR)structure, in accordance with some embodiments.

FIG. 3 is a layout diagram of an IC with an HPR structure, in accordancewith some embodiments.

FIG. 4 is a schematic diagram of an IC of an HPR structure having twoburied power rail structures, in accordance with some embodiments.

FIG. 5 is layout diagram of an IC of an HPR structure having two buriedpower rail structures, in accordance with some embodiments.

FIG. 6 is a flowchart of a method of forming the HPR structure of FIG.1, in accordance with one or more embodiments.

FIGS. 7A-7F are diagrams of an HPR structure at various manufacturingstages corresponding to the method of FIG. 4, in accordance with one ormore embodiments.

FIG. 8 is a flowchart of a method of forming the HPR structure of FIG.3, in accordance with one or more embodiments.

FIGS. 9A-9F are diagrams of an HPR structure at various manufacturingstages corresponding to the method of FIG. 6, in accordance with someembodiments.

FIG. 10 is a flowchart of a method of generating a cell layout design ofan IC with the HPR structure of FIG. 1 or FIG. 3, in accordance with oneor more embodiments.

FIG. 11 is a schematic view of a system for designing an IC layoutdesign, in accordance with some embodiments.

FIG. 12 is a block diagram of an IC manufacturing system, and an ICmanufacturing flow associated therewith, in accordance with someembodiments.

DETAILED DESCRIPTION

The following disclosure provides many different embodiments, orexamples, for implementing different features of the provided subjectmatter. Specific examples of components, values, operations, materials,arrangements, or the like, are described below to simplify the presentdisclosure. These are, of course, merely examples and are not intendedto be limiting. Other components, values, operations, materials,arrangements, or the like, are contemplated. For example, the formationof a first feature over or on a second feature in the description thatfollows may include embodiments in which the first and second featuresare formed in direct contact, and may also include embodiments in whichadditional features may be formed between the first and second features,such that the first and second features may not be in direct contact. Inaddition, the present disclosure may repeat reference numerals and/orletters in the various examples. This repetition is for the purpose ofsimplicity and clarity and does not in itself dictate a relationshipbetween the various embodiments and/or configurations discussed.

Further, spatially relative terms, such as “beneath,” “below,” “lower,”“above,” “upper” and the like, may be used herein for ease ofdescription to describe one element or feature's relationship to anotherelement(s) or feature(s) as illustrated in the figures. The spatiallyrelative terms are intended to encompass different orientations of thedevice in use or operation in addition to the orientation depicted inthe figures. The apparatus may be otherwise oriented (rotated 90 degreesor at other orientations) and the spatially relative descriptors usedherein may likewise be interpreted accordingly.

The present disclosure describes an implementation of an integratedcircuit (IC) using a hybrid power rail (HPR) structure for providingpower efficiently to the operational components of the IC. The HPRstructure allows for power to be provided from the top and bottom of thesubstrate incorporating the HPR structure compared to power railstructures that only provide power from one side of the substrate.Moreover, the HPR structure reduces the effects of shorting associatedwith Through Silicon Via (TSV) critical dimensions (CD) and TSV overlayissues associated with buried power rails.

FIG. 1 is a block diagram of an IC 100 having a semiconductor device101, in accordance with some embodiments. In FIG. 1, semiconductordevice 101 includes, among other things, a circuit macro (hereinafter,macro) 102. In some embodiments, macro 102 is an SRAM macro. In someembodiments, macro 102 is a macro other than an SRAM macro. Macro 102includes, among other things, one or more HPR arrangements 104A and104B. An example of a layout diagram which is used to fabricate an HPRarrangement 104A with a single buried power rail includes the layoutdiagram of FIG. 3. An example of a layout diagram which is used tofabricate an HPR arrangement 104B with two buried power rails includesthe layout diagram of FIG. 5.

FIG. 2A is a perspective view of an HPR structure 200, in accordancewith some embodiments. The HPR structure 200 is on, and at leastpartially in, a substrate 203 (FIG. 2C) and includes a first power rail202, a second power rail 204, and a device structure 206. In one or moreembodiments, device structure 206 includes more than one devicestructure. Each power rail is configured to supply a voltage to devicestructure 206. The second power rail 204 is also referred to as a buriedpower rail with reference to location of the power rail in the substratein relation to device structure 206. The substrate has a front side anda back side opposite the front side. For clarity and ease ofunderstanding, the substrate is not shown in FIG. 2A.

The first power rail 202 is a conductive structure positioned on thefront side of the substrate and configured to supply a first voltageVDD, and the second power rail 204 is a buried power rail positioned onthe front side of the substrate and configured to supply a secondvoltage VSS. In at least some embodiments, the second power rail 204 ispositioned in the front side of the substrate. The HPR structure 200also includes a through silicon via (TSV) 208 connected with the buriedpower rail 204 and extending through the back side of the substrate. TSV208 is configured to supply a voltage to buried power rail 204. Firstvoltage VDD differs from second voltage VSS. In some embodiments, thefirst power rail 202 is configured to supply second voltage VSS and thesecond power rail 204 is configured to supply first voltage VDD.

The first power rail 202 and the second “buried” power rail 204 extendin substantially parallel rows in a first direction (X-axis). The buriedpower rail 204 is embedded in the substrate and is separated from thefirst power rail 202 in a second direction (Y-axis) different from thefirst direction. The second direction (Y-axis) is substantiallyperpendicular to the first direction (X-axis). The buried power rail 204is below the level of the first power rail 202 in a third direction(Z-axis) that is substantially perpendicular to both the first andsecond directions.

Device structure 206 is positioned between the first power rail 202 andthe buried power rail 204. In at least one embodiment, device structure206 includes one or more cells, also referred to as standard cells insome embodiments. In various embodiments, a cell includes a logic gatecell, a custom cell, an engineering change order cell, a memory cell, oranother suitable circuit module. In some embodiments, a logic gate cellincludes an AND, OR, NAND, NOR, XOR, INV, AND-OR-Invert (AOI),OR-AND-Invert (OAI), MUX, Flip-flop, BUFF, Latch, delay, or clock cell.In some embodiments, a memory cell includes a static random accessmemory (SRAM), a dynamic RAM (DRAM), a resistive RAM (RRAM), amagnetoresistive RAM (MRAM) or read only memory (ROM).

In various embodiments, a cell includes one or more passive and/oractive devices. Examples of active devices include, but are not limitedto, transistors and diodes. Examples of transistors include, but are notlimited to, metal oxide semiconductor field effect transistors (MOSFET),complementary metal oxide semiconductor (CMOS) transistors, bipolarjunction transistors (BJT), high voltage transistors, high frequencytransistors, p-channel and/or n-channel field effect transistors(PFETs/NFETs), etc.), FinFETs, and planar MOS transistors with raisedsource/drain. Examples of passive devices include, but are not limitedto, capacitors, inductors, fuses, and resistors.

Moreover, device structure 206 defines a region that includes a pitch atwhich the TSV 208 provides power via buried power rail 204. In a givenimplementation, a contacted poly pitch (CPP) defines a minimumcenter-to-center space between gates of adjacent transistors of one ormore cell structures that are coupled to a single TSV structure, and thepitch of the TSV 208 is defined as a multiple of the CPP. In someembodiments, more than one TSV 208 is electrically coupled with buriedpower rail 204 in order to provide a voltage to more than one devicestructure 206.

TSV 208 is in the substrate and configured to electrically connect theburied power rail 204 to a backside power source configured to supplythe second voltage VSS. TSV 208 extends through the back side of thesubstrate to electrically connect with buried power rail 204. The buriedpower rail 204 is electrically connected with and positioned on the TSV208 and configured to receive the second voltage VSS. TSV 208 issubstantially larger in plan view dimensions and pitch than in otherapproaches lacking the HPR structure. In some embodiments, TSV 208 isdimensioned to be greater than two times the height of a cell height ofa cell of device structure 206. In some embodiments, TSV 208 has alength ranging from 250 nanometers (nm) to 500 nm. In some embodiments,TSV 208 has a width ranging from 250 nm to 500 nm. In some embodiments,TSV 208 has a height ranging from 1 micrometer (μm) to 2μm. In someembodiments, TSV 208 has a pitch ranging from 16 to 60 CPP.]

In power grid structures, there is a likelihood of TSV overlay errorswhen the TSV is not aligned with a power rail which can result in shortcircuits. The TSV CDs are the sizing dimensions to ensure reliablemanufacturing and functioning of TSV structures. TSV CDs include TSVetch depth, TSV diameter, and TSV etch profile. If one or more of theTSV CDs are outside manufacturing limits, the TSV will potentially causea short circuit of a power grid structure. Multiple TSV structuresincrease the likelihood of TSV overlay and TSV CD issues which resultsin an increased likelihood of a short circuited power grid.

In some embodiments, HPR structure 200 lowers the risks involving TSVCDs by using a single TSV 208 as described above. Moreover, the HPRstructure 200 does not require aligning multiple buried power rails withmultiple TSVs thereby reducing the likelihood of TSV overlay errors. Theburied power rail 204 is aligned with the TSV structure 208 lowering thechances of producing TSV overlay errors. The first power rail 202 doesnot contact the TSV 208. Moreover, the TSV 208 is larger in comparisonto TSVs used in other approaches lacking the HPR structure. TSV CDs andTSV overlay limit the size of TSV structures used in power gridstructures.

The HPR structure 200 combines the first power rail 202 with the second“buried” power rail 204 to provide power to device structure 206.Moreover, in some embodiments, the HPR structure 200 utilizes only asingle TSV structure 208 for backside power minimizing the effects ofTSV CD and TSV overlay errors seen with other power grid structureshaving multiple TSV structures wherein alignment and overlay errorsresult in short circuits.

FIG. 2B is a perspective view of HPR structure 200 including furtherdetails regarding the implementation of a number of passive and activedevices. In particular, the device structure 206 includes a number offirst metal tracks 210 a-210 d (collectively referred to as first metaltracks 210). The first metal tracks 210 a-210 d extend in substantiallyparallel rows in the first direction (X-axis). Active regions 211 a-211b (collectively referred to as active regions 211) each overlap aportion of and are positioned below the first metal tracks 210 a and 210c. The active regions 211 extend substantially parallel along the firstdirection (X-axis). Metal contact diffusion structures 212 arepositioned on active regions 210 a-210 b to form the passive or activedevices of the device structure 206. The metal contact diffusionstructures 212 extend in substantially parallel columns in the seconddirection (Y-axis). Polysilicon gate structures 214 a-214 f(collectively referred to as polysilicon gate structures 214) arepositioned beneath, along the Z-axis, the first power rail 202. Thepolysilicon gate structures 214 extend in substantially parallel columnsin the second direction and substantially parallel to the metal contactdiffusion structures 212. The regions between each of the polysilicongate structures 214 a-214 e are cell regions 216. HPR structure 200includes 5 cell regions 216 and 4 first metal tracks 210. The activeregions 210 are positioned beneath, along the Z-axis, the polysilicongate structures. In some embodiments, device structure 206 includes moreor less than 5 cell regions 216. In various embodiments, one or morecell regions 216 combine to form a given cell as discussed above withrespect to device structure 206.

HPR structure 200 includes a via structure 218 that electricallyconnects the first power rail 202 to one of the metal contact diffusionstructures 212. Via structures electrically connect a select number ofthe first metal tracks 210 to a certain number of the metal contactdiffusion structures 212. Moreover, via structures electrically connecta certain number of the polysilicon gate structures 214 b-214 e to thefirst metal tracks 210.

In some embodiments, via structure 218 is a square via. In someembodiments, via structure 218 is a hole etched in an interlayerdielectric that is filled with a metal. In some embodiments, viastructure 218 is a buried via. In some embodiments, via structure 218 isreplaced with layered metal pairs.

A via structure 226 electrically connects a first conductive structure228 to the first power rail 202. A via structure 230 is on the firstconductive structure 228. The via structure 230 electrically connects asecond conductive structure 232 to the first conductive structure 228.The first conductive structure 228 extends along the second direction,and the second conductive structure 232 extends along the firstdirection. The first conductive structure 228 and the second conductivestructure 232 are electrically connected to the first power rail 202configured to supply the first voltage VDD. The arrangement of the viastructure 226, the first conductive structure 228, the via structure230, and the second conductive structure 232 extends in a thirddirection (Z-axis) perpendicular to the first direction and seconddirection. The first conductive structure 228 and the second conductivestructure 232 extends above the transistor plane that includes thedevice structure 206. In some embodiments, the first conductivestructure 228 and second conductive structure 232 reside in differentmetallization layers of the semiconductor.

In some embodiments, the first conductive structure 228 and the secondconductive structure 232 are in different metallization layers. In someembodiments, additional conductive structures and via structures areadded after the second conductive structure 232. In some embodiments,via structures 226 and 230 are square vias. In some embodiments, viastructures 226 and 230 are holes etched in an interlayer dielectric thatare filled with a metal. In some embodiments, via structures 226 and 230are buried vias. In some embodiments, via structures 226 and 230 aredifferent from each other in shape, dimensions, and materials. In someembodiments, via structures 226 and 230 are replaced with layered metalpairs.

FIG. 2C is a cross-sectional view of the HPR structure 200 of FIG. 2B.In particular, FIG. 2C is the cross-sectional view of the Y-cut of theHPR structure 200, as shown in FIGS. 2A and 2B. A substrate 203surrounds the buried power rail 204 and the TSV 208. The polysilicongate structure 214 a is above the buried power rail 204 and below thefirst power rail 202. FIG. 2C includes the first via structure 226 onthe first power rail 202 and the first conductive structure 228 on thefirst via structure 226. The second via structure 226 is on the firstconductive structure 228. The two TSVs 208 each provide power to theirrespective power rails 204. A separation (not labeled) between the TSVs208 in the second direction (Y-axis) is sufficient to avoid overlayerrors or TSV CD issues. In some embodiments, the separation between theTSVs in the second direction ranges from 0.5 μm to 5.0 μm.

FIG. 2D is another cross-sectional view of the HPR structure 200 of FIG.2B. In particular, FIG. 2D is the cross-sectional view of the X-cut ofthe HPR structure 200, as shown in FIG. 2B. Similar to FIG. 2C, thesubstrate 203 surrounds the buried power rail 204 and the TSV 208. Theburied power rail 204 is on the TSV 208. The long axis of the buriedpower rail 204 extends along the first direction (X-axis). A separationnot labeled) between the TSVs 208 in the first direction (X-axis) issufficient to avoid overlay errors or TSV CD issues. In someembodiments, the separation between the TSVs in the first directionranges from 0.5 μm to 5.0 μm.

FIG. 3 is a layout diagram 300 of an integrated circuit (IC) with thehybrid power rail (HPR) structure 200 of FIG. 2A, in accordance withsome embodiments. The layout 300 includes a first power rail layoutpattern 302 (corresponding to first power rail 202), a buried power raillayout pattern 304 (corresponding to buried power rail 204), a firstdevice pattern 306 (corresponding to device structure 206), a number ofvia patterns 310, 312, 314, 316, 318, 320, 321, and 323, and metal trackpatterns 322. The long axis of the first power rail layout pattern 302and the buried power rail layout pattern 304 extends along a firstdirection (X-axis). The first power rail layout pattern 302 correspondsto a conductive structure configured to provide a first supply voltageVDD. The buried power rail layout pattern 304 corresponds to aconductive structure configured to provide a second supply voltage VSS.The first power rail pattern 302 and the buried power rail pattern 304and extend in substantially parallel rows in the first direction(X-axis). The buried power rail 304 is separated from the first powerrail 302 in a second direction (Y-axis) different and substantiallyperpendicular to the first direction (X-axis).

The first device pattern 306 is between the power rail pattern 302 andthe buried power rail pattern 304. The first device pattern 306 includesa number of first metal track patterns 322. The first metal trackpatterns 322 extend in substantially parallel rows in the firstdirection (X-axis). The metal contact diffusion patterns 325 are onactive region patterns 334 and 336 and extend substantially parallel incolumns along the second direction (Y-axis). The regions between each ofthe polysilicon gate patterns 324, 326, 328, 330, 331, and 332 are cellregions 329. There are 5 cell regions 329 and 4 metal tracks patterns322. In some embodiments, there are more than 5 cell regions in thefirst device pattern 306.

Via patterns 308, 310, 312, 314, and 318, are between a select number ofthe first metal track patterns 322 and a select number of the metalcontact diffusion patterns 325. Via patterns 316, 320, 321, and 323 arebetween the polysilicon gate patterns 326, 328, 330, and 331 and thefirst metal track patterns 322. The first device pattern 306 representsa number of active and passive devices formed on the active regionpatterns 334 and 336.

In some embodiments, via patterns 308, 310, 312, 314, 316, 318, 320,321, and 323 are square via patterns. In some embodiments, via patterns308, 310, 312, 314, 316, 318, 320, 321, and 323 are buried via patterns.In some embodiments, via patterns 308, 310, 312, 314, 316, 318, 320,321, and 323 are different from each other in shape and size. In someembodiments, via patterns 308, 310, 312, 314, 316, 318, 320, 321, and323 are replaced with layout patterns of layered metal pairs.

A TSV pattern 338 is provided where the buried power rail pattern 304 ispositioned on the TSV pattern 336. The first power rail pattern 302 isnot in contact with the TSV pattern 338.

In some embodiments, the layout diagram 300 includes a pick-up cellpattern (not shown) corresponding to a pick-up cell structure asdiscussed below with respect to FIG. 4.

FIG. 4 is a perspective view of an HPR structure 400 having two buriedpower rail structures, in accordance with some embodiments. The HPRstructure 400 includes a first buried power rail 402 and a second buriedpower rail 404 formed in a substrate. Moreover, the HPR structure 400includes a first device structure 406 having passive or active devicesand via structures 410, 412, 414, 416, 418, 420, 422, and 424 toestablish electrical connections.

The first buried power rail 402 is configured to provide a first supplyvoltage VDD through a pick-up cell structure 446 or other electricalcontact as discussed below, and the second buried power rail 404 isconfigured to provide a second supply voltage VSS. The first buriedpower rail 402 and the second buried power rail 404 are arrangedsubstantially in parallel in rows. The second buried power rail 404 isconfigured to provide a second supply voltage VSS different from thefirst supply voltage VDD. The long axis of the first buried power rail402 and the second buried power rail 404 extends along a first direction(X-axis). The second buried power rail 404 is separated from the firstpower rail 402 in a second direction (Y-axis) different andsubstantially perpendicular to the first direction (X-axis).

The first device structure 406 is between the first buried power rail302 and the second buried power rail 404. The first device structure 406is located above the first buried power rail 402 and the second buriedpower rail 404. The first device structure 406 includes a number offirst metal tracks 426. The first metal tracks 426 are arrangedsubstantially in parallel in columns and extending along the firstdirection (X-axis). Active regions 428 and 430 are at selectivelocations in the first device structure 406 to form a number of activeor passive devices of the first device structure 406. The active regions428 and 430 are arranged and extend substantially parallel in rows alongthe first direction (X-axis). A number of contact metal diffusionstructures 431 are on the active regions 428 and 430 to form variouspassive and active structures. The contact metal diffusion structures431 are arranged in columns and extend substantially in parallel in thesecond direction (Y-axis).

Polysilicon gate structures 432, 434, 436, 438, 440, and 442 arearranged substantially in parallel in columns and extending along thesecond direction. The regions between polysilicon gate structures 432,434, 436, 438, 440, and 442 form cell regions 429. In this case, thereare 5 cell regions and 4 metal tracks. In some embodiments, there aremore or less than 5 cell regions in the first device 406.

Via structures 410, 414, 416, and 424, electrically connect a selectnumber of the first metal tracks 426 to a select number of the metalcontact diffusion structures 431. Via structures 412, 418, 420, 422electrically connect the polysilicon gate structures 434, 436, and 438to the first metal tracks 426. First device structure 406 represents anumber of active and passive devices formed therein.

In some embodiments, via structures 410, 412, 414, 416, 418, 420, 422,and 424 are square vias. In some embodiments, via structures 410, 412,414, 416, 418, 420, 422, and 424 are holes etched in an interlayerdielectric that is filled with a metal. In some embodiments, viastructures 410, 412, 414, 416, 418, 420, 422, and 424 are buried vias.In some embodiments, via structures 410, 412, 414, 416, 418, 420, 422,and 424 are different from each other in shape, size, and materials. Insome embodiments, via structures 410, 412, 414, 416, 418, 420, 422, and424 are replaced with layered metal pairs.

A TSV 408 is configured to connect the second buried power rail 404 tothe power source VSS. The first buried power rail 402 does not come intocontact with the TSV 408. The first buried power rail 402 and the secondburied power rail 404 are each configured to be embedded in thesubstrate. The height ha of the first buried power rail 402 and theheight hb of the second buried power rail 404 are different, wherehb>ha. A protective layer 466 is positioned beneath the first buriedpower rail 402 to protect the bottom surface of the first buried powerrail 402 from damage and coming into contact with the TSV 408. In someembodiments, the protective layer 466 is an insulator. In someembodiments, the protective layer 466 is not required.

By using different heights, ha and hb, of the first buried power rail402 and the second buried power rail 404, the issues regarding shortcircuiting caused by TSV overlay errors and TSV CDs are minimized. Theheight ha is selected so that the first buried power rail 402 does notcome into contact or is electrically coupled to TSV 408 thereby reducingthe risk of a short circuit. The height hb is selected so that thesecond buried power rail 404 is electrically coupled to TSV 408. Thesecond buried power rail 404 is the only structure that is to beelectrically coupled to the TSV 408 for backside power, which alleviatesthe issues of misalignment associated with TSV overlay errors. If thefirst buried power rail 402 is also electrically coupled to the TSV 408,then overlay errors and TSV CD issues will arise because the secondburied power rail is the only buried power rail specifically configuredto be electrically coupled to TSV 408. Moreover, in some embodiments,HPR structure 400 includes a single TSV structure in order to minimizeissues regarding TSV CDs.

In the embodiment depicted in FIG. 4, the HPR structure 400 includes thepick-up cell structure 446 configured to extend the HPR structure 400along a third direction (Z-axis) perpendicular to the first directionand the second direction, thereby providing a portion of a conductivepath between the first buried power rail 402 and an external voltagesupply (not shown) configured to the first supply voltage VDD asdiscussed below.

The pick-up cell structure 446 includes at least one contact metaldiffusion structure 452 electrically connected to the first buried powerrail 402. One or more metal tracks 450 are electrically connected to theat least one contact metal diffusion structure 452 through at least onevia structure (not shown). The one or more metal tracks 450 are arrangedsubstantially in parallel in rows and extending along the firstdirection (X-axis). The pick-up cell structure 446 also includespolysilicon gate structure 442 discussed above and polysilicon gatestructures 454 and 456 arranged substantially in parallel in columns andextending along the second direction (Y-axis). At least one viastructure 458 is positioned on the one or more metal tracks 450, andelectrically connects a first conductive structure 460 to the one ormore metal tracks 450. The long axis of the first conductive structure460 extends along the second direction (Y-axis). A via structure 462 ispositioned on the first conductive structure 460, and electricallyconnects the first conductive structure 460 to a second conductivestructure 464. The long axis of the second conductive structure 464extends along the first direction (X-axis). The second conductivestructure 464 is configured to carry the first supply voltage VDD.

By the configuration discussed above, the pick-up cell structure 446provides an electrical connection between the external voltage supplyand the first buried power rail 402.

In some embodiments, the long axis of the first conductive structure 460extends along the first direction (X-axis). In some embodiments, thelong axis of the second conductive structure 464 extends along thesecond direction (Y-axis). In some embodiments, the power connectionsare a hole, a trench, or both.

FIG. 5 is a layout diagram 500 of an integrated circuit (IC) with thehybrid power rail (HPR) structure 400 of FIG. 4, in accordance with someembodiments. The layout 500 includes a first buried power rail pattern502 and a second buried power rail pattern 504. Moreover, the layout 500includes a first device pattern 506, for representing passive or activedevices, and via patterns 510, 512, 514, 516, 518, 520, 522, and 524 torepresent electrical connections.

The first buried power rail pattern 502 and the second buried power railpattern 504 are arranged in substantially parallel rows. The long axisof the first buried power rail pattern 502 and the second buried powerrail pattern extends 504 along a first direction (X-axis). The secondpower rail pattern 504 is separated from the first power rail pattern502 in a second direction (Y-axis) different from the first direction.

The first device pattern 506 is between the first power rail pattern 502and the second power rail pattern 504. The first device pattern 506 isabove the first buried power rail pattern 502 and the second buriedpower rail pattern 504. The first device pattern 506 includes a numberof first metal track patterns 526. The first metal track patterns 526are arranged in substantially parallel columns and extending along thefirst direction (X-axis). Active region patterns 528 and 530 are atselective locations in the first device pattern 506 to form a number ofactive or passive devices. The active region patterns 528 and 530 arearranged in substantially parallel rows and extend along the firstdirection (X-axis). A number of contact metal diffusion patterns 531 areon the active region patterns 528 and 530 to form various passive andactive structures in the first device pattern 506. The contact metaldiffusion patterns 531 are arranged in substantially parallel columnsand extending in the second direction (Y-axis).

Polysilicon gate patterns 532, 534, 536, 538, 540, and 542 are arrangedin substantially parallel columns and extending in the second direction.The regions between polysilicon gate patterns 532, 534, 536, 538, 540,and 542 define cell regions 529. In this case, there are 5 cell regionsand 4 metal track patterns. In some embodiments, there are more or lessthan 5 cell regions formed in the first device pattern 506.

Via patterns 510, 514, 516, and 524, are positioned between a selectnumber of the first metal track patterns 526 and a select number of themetal contact diffusion patterns 531. Via patterns 512, 518, 520, 522are positioned between the polysilicon gate patterns 434, 436, and 438and the first metal track patterns 426.

In some embodiments, via patterns 510, 512, 514, 516, 518, 520, 522, and524 are square via patterns. In some embodiments, via patterns 510, 512,514, 516, 518, 520, 522, and 524 are patterns of holes etched in aninterlayer dielectric that is filled with a metal. In some embodiments,via patterns 510, 512, 514, 516, 518, 520, 522, and 524 are buried viapatterns. In some embodiments, via patterns 510, 512, 514, 516, 518,520, 522, and 524 are different from each other in shape and size. Insome embodiments, via patterns 510, 512, 514, 516, 518, 520, 522, and524 are buried via patterns. In some embodiments, the via patterns 510,512, 514, 516, 518, 520, 522, and 524 are replaced with patterns oflayered metal pairs.

The first buried power rail pattern 502 and the second buried power railpattern 504 are each on the TSV pattern 508. The height of the firstburied power rail pattern 502 is different from the height of the secondburied power rail pattern 504.

In some embodiments, the layout diagram 500 includes a pick-up cellpattern (not shown) corresponding to a pick-up cell structure asdiscussed above with respect to FIG. 4.

FIG. 6 is a flowchart of a method 600 of forming the HPR structure 200(FIG. 2B), in accordance with one or more embodiments. FIGS. 7A-7F arediagrams of the HPR structure 200 at various manufacturing stagescorresponding to the operations of method 600, in accordance with someembodiments. Method 600 is executable to form HPR structure 200,discussed above with respect to FIGS. 2A-2D, and HPR structure 700 isusable as HPR structure 200, in some embodiments.

The sequence in which the operations of method 600 are depicted in FIG.6 is for illustration only; the operations of method 600 are capable ofbeing executed in sequences that differ from that depicted in FIG. 6. Insome embodiments, operations in addition to those depicted in FIG. 6 areperformed before, between, during, and/or after the operations depictedin FIG. 6.

At operation 602, a stop layer 702 is formed before the devicestructures 706 are formed. The stop layer 702 is formed by depositing,using chemical vapor deposition or the like, silicon nitride, siliconoxy-nitride, silicon carbide, or carbon-doped silicon nitride or thelike. Details regarding an embodiment of a process usable to form a stoplayer are found in U.S. Pat. No. 9,589,803 issued Mar. 7, 2017, which isincorporated herein by reference in its entirety. The stop layer 702 isformed on a substrate 704, as shown in FIG. 7A. Afterwards, the devicestructures 706 are formed on the substrate 704.

At operation 604, a trench process is used to form a trench in substrate704, as shown in FIG. 7B. The trench process involves etching on thesubstrate 704 using techniques including wet etching, dry etching,sputtering etching or the like. Details regarding an embodiment of aprocess usable to form a trench are found in U.S. Pat. No. 10,115,679issued Mar. 13, 2018, which is incorporated herein by reference in itsentirety. After the trench is formed, conductive material is depositedin the trench to form the buried power rail (BPR) 708.

At operation 606, local metal connections 710 are formed for the buriedpower rail 708 and the device structures 706, as shown in FIG. 7C. Thelocal metal connections 710 are used to form the source and drain of thedevice structures 706.

At operation 608, the polysilicon gate structures 712 are formed on thesubstrate 704, as shown in FIG. 7D. The polysilicon gate structures areformed by depositing polysilicon in gate strips. The gate strips areformed using processing operations of oxide deposition, polysilicondeposition, etching and sidewall formation before or after active sourceand drain diffusion implantation, thermal annealing, or other suitableprocess. Details regarding an embodiment of a process usable to form apolysilicon gate structure are found in U.S. Pat. No. 8,698,205 issuedApr. 15, 2014, which is incorporated herein by reference in itsentirety. The polysilicon gate structures 712 are between the devicestructures 706 and substrate 704. The first power rail 714 and metaltracks 716 are formed. A number of the metal tracks 716 are on viastructures 720 for electrical connections with the device structure 706.The first power rail 714 is connected to a via structure 718 to providepower supply voltage VDD. The first power rail 714 and the metal tracks716 reside in a first metallization layer M0.

At operation 610, second metal tracks 722 are formed using a back end ofline (BEOL) process, as shown in FIG. 7E. The BEOL process involvesforming the metal wiring between the device structures 706 in order tointerconnect them including forming contacts, interconnect wires, viastructures, and dielectric structures. The second metal tracks 722 areon a via structure 724 connected to the first power rail 714. In otherembodiments, the BEOL process is used to form additional conductivemetal structures after the second metal tracks 722 have been formed. Thesecond metal tracks reside in a second metallization layer M1.

At operation 612, the through silicon via (TSV) 726 is formed in thesubstrate 704, as shown in FIG. 7F. The substrate 704 is etched andlined with a barrier against copper diffusion. A seed layer is depositedprior to filling the etched region with copper using some form ofaqueous deposition or the like to form TSV 726. Details regarding anembodiment of a process usable to form a TSV are found in U.S. Pat. No.9,087,878 issued Jul. 21, 2015, which is incorporated herein byreference in its entirety. The second BPR 710 is in contact with andelectrically coupled to the TSV 726 to provide the backside power.

FIG. 8 is a flowchart of a method 800 of forming HPR structure 400 (FIG.4), in accordance with one or more embodiments. FIGS. 9A-9F are diagramsof the HPR structure 400 at various manufacturing stages correspondingto the operations of method 800, in accordance with some embodiments.Method 800 is operable to form HPR structure 400, discussed above withrespect to FIG. 4, and HPR structure 900 is usable as HPR structure 400,in some embodiments.

The sequence in which the operations of method 800 are depicted in FIG.8 is for illustration only; the operations of method 800 are capable ofbeing executed in sequences that differ from that depicted in FIG. 8. Insome embodiments, operations in addition to those depicted in FIG. 8 areperformed before, between, and/or after the operations depicted in FIG.8.

At operation 802, a stop layer 902 is formed before device structures906 are formed, as shown in FIG. 9A. The stop layer 902 is formed bydepositing on the substrate 904 silicon nitride, silicon oxy-nitride,silicon carbide, or carbon-doped silicon nitride or the like. Detailsregarding an embodiment of a process usable to form a stop layer arefound in U.S. Pat. No. 9,589,803 issued Mar. 7, 2017, which isincorporated herein by reference in its entirety. Afterwards, the devicestructures 906 are formed on the substrate 904 using the device process.

At operation 804, a trench process is used to form a first trench in thesubstrate 904. The trench process involves etching the substrate 704using techniques including wet etching, dry etching, sputtering etchingo the like. Details regarding an embodiment of a process usable to forma trench are found in U.S. Pat. No. 10,115,679 issued Mar. 13, 2018,which is incorporated herein by reference in its entirety. Once thefirst trench is formed, conductive material is deposited in the firsttrench to form the first BPR 908. The first BPR 908 includes a heightha, as shown in FIG. 9B.

At operation 806, the trench process is used to form a second trench.After the second trench is formed, conductive material is deposited inthe second trench to form the second BPR 910. The second BPR 910includes a height hb. The heights ha and hb are not equivalent forreasons discussed herein to minimize the risk of short circuit, as shownin FIG. 9C.

At operation 808, local metal connections 912 are formed for the firstburied power rail 908, the second buried power rail 910, and the devicestructures 906. The polysilicon gate structures 914 are formed on thesubstrate 904. A certain number of device structures 906 are within thepolysilicon gate structures 914. The local metal connections 912 areused to form the source and drain of the device structures 906, as shownin FIG. 9D.

At operation 810, the first metal tracks 916 are formed using a BEOLprocess, as shown in FIG. 9E. The BEOL process involves forming themetal wiring between the device structures 906 in order to interconnectthem including forming contacts, interconnect wires, via structures, anddielectric structures. A select number of the first metal tracks 916 areon via structures 918 for electrical connections. Second metal tracks920 are formed using the BEOL process. A select number of the secondmetal tracks 920 are positioned on via structures 922 that are connectedto the select number of first metal tracks 916. Moreover, the firstmetal tracks 916 reside in a first metallization layer and the secondmetal tracks 920 reside in a second metallization layer. In otherembodiments, the BEOL process is used to form additional metal tracksafter the second metal tracks 920.

At operation 812, a TSV 924 is formed in the substrate 904. Thesubstrate 904 is etched and lined with a barrier against copperdiffusion. A seed layer is deposited prior to filling the etched regionwith copper using some form of aqueous deposition or the like to formTSV 924. Details regarding an embodiment of a process usable to form aTSV are found in U.S. Pat. No. 9,087,878 issued Jul. 21, 2015, which isincorporated herein by reference in its entirety. The TSV 924 is incontact with and electrically coupled to the second BPR 910 to providethe backside power, as shown in FIG. 9F.

FIG. 10 is a flowchart of a method 1000 of generating a cell layoutdesign of an IC with the HPR structure 300 or 500 (FIG. 3 or FIG. 5), inaccordance with one or more embodiments.

In step 1002, the method 1000 includes generating, by a processor (e.g.,processor 1102 of FIG. 11), a cell layout design of the integratedcircuit, and manufacturing the integrated circuit based on the celllayout design.

In step 1004, the method 1000 includes generating the cell layout designcomprises generating a first power rail layout pattern, such as 302 or502 (FIG. 3 or FIG. 5), extending in a first direction (FIGS. 3 and 5,X-axis). In some embodiments, the first power rail layout patterncorresponds to fabricating a first power rail that is embedded in asubstrate and configured to provide a first supply voltage.

In step 1006, the method 1000 includes generating the cell layout designfurther comprises generating a second power rail layout pattern, such as304 or 504 (FIG. 3 or FIG. 5), extending in the first direction, such asthe X-axis (FIG. 3 or FIG. 5), and being separated from the first powerrail layout pattern in a second direction, such as the Y-axis (FIG. 3 orFIG. 5), different from the first direction. In some embodiments, thesecond power rail layout pattern corresponds to fabricating a secondpower rail embedded in the substrate and configured to provide a secondsupply voltage different from the first supply voltage.

In step 1008, the method 1000 includes generating the cell layout designfurther comprises generating a set of device layout patterns, such as306 or 506 (FIG. 3 or FIG. 5), positioned between the first power raillayout pattern and the second power rail layout pattern, being locatedabove the first power rail layout pattern and the second power raillayout pattern. In some embodiments, the set of device layout patternscorresponds to fabricating a set of devices.

In step 1010, the method 1000 includes generating the cell layout designfurther comprises generating a through silicon via layout pattern, suchas 338 or 508 (FIG. 3 or FIG. 5), corresponding to fabricating a throughsilicon via. In some embodiments, the through silicon via extendsthrough the backside of the substrate, and is electrically coupled tothe second power rail.

In step 1012, the method 1000 includes generating the cell layout designfurther comprises generating a conductive structure layout pattern, suchas 242 or 360 (FIG. 2A or FIG. 4), extending in at least the firstdirection or the second direction, being above the set of device layoutpatterns, the first power rail layout pattern and the second power raillayout pattern. In some embodiments, the conductive structure layoutpattern corresponds to fabricating a conductive structure electricallycoupled to the first power rail.

In step 1014, the method 1000 includes generating the cell layout designfurther including generating a via layout pattern, such as via 240 or458 (FIG. 2A or FIG. 4), positioned between the first power rail layoutpattern and the conductive structure layout pattern, and correspondingto fabricating a via. In some embodiments, the via electrically couplesthe first power rail to the conductive structure.

In some embodiments, the integrated circuit further includes one or morefirst cells.

In some embodiments, a set of active region layout patterns is usable tomanufacture a corresponding set of active regions of IC. In someembodiments, set of active regions of IC is referred to as an activeregion of the IC which defines the source or drain diffusion regions ofthe IC.

FIG. 11 is a schematic view of a system 1100 for designing an IC layoutdesign in accordance with some embodiments. In some embodiments, system1100 generates or places one or more IC layout designs described herein.System 1100 includes a hardware processor 1102 and a non-transitory,computer readable storage medium 1104 encoded with, i.e., storing, thecomputer program code 1106, i.e., a set of executable instructions.Computer readable storage medium 1104 is configured for interfacing withmanufacturing machines for producing the integrated circuit. Theprocessor 1102 is electrically coupled to the computer readable storagemedium 1104 via a bus 1108. The processor 1102 is also electricallycoupled to an I/O interface 1110 by bus 1108. A network interface 1112is also electrically connected to the processor 1102 via bus 1108.Network interface 1112 is connected to a network 1114, so that processor1102 and computer readable storage medium 1104 are capable of connectingto external elements via network 1114. The processor 1102 is configuredto execute the computer program code 1106 encoded in the computerreadable storage medium 1104 in order to cause system 1100 to be usablefor performing a portion or all of the operations as described in method1000.

In some embodiments, the processor 1102 is a central processing unit(CPU), a multi-processor, a distributed processing system, anapplication specific integrated circuit (ASIC), and/or a suitableprocessing unit.

In some embodiments, the computer readable storage medium 1104 is anelectronic, magnetic, optical, electromagnetic, infrared, and/or asemiconductor system (or apparatus or device). For example, the computerreadable storage medium 904 includes a semiconductor or solid-statememory, a magnetic tape, a removable computer diskette, a random accessmemory (RAM), a read-only memory (ROM), a rigid magnetic disk, and/or anoptical disk. In some embodiments using optical disks, the computerreadable storage medium 904 includes a compact disk-read only memory(CD-ROM), a compact disk-read/write (CD-R/W), and/or a digital videodisc (DVD).

In some embodiments, the storage medium 1104 stores the computer programcode 1106 configured to cause system 1100 to perform method 1000. Insome embodiments, the storage medium 1104 also stores information neededfor performing method 1000 as well as information generated duringperforming method 1000, such as layout design 1116 and user interface1118, and/or a set of executable instructions to perform the operationof method 1000. In some embodiments, layout design 1116 comprises one ormore of layout designs.

In some embodiments, the storage medium 1104 stores instructions (e.g.,computer program code 1106) for interfacing with manufacturing machines.The instructions (e.g., computer program code 1106) enable processor1102 to generate manufacturing instructions readable by themanufacturing machines to effectively implement method 1000 during amanufacturing process.

System 1100 includes I/O interface 1110. I/O interface 1110 is coupledto external circuitry. In some embodiments, I/O interface 1110 includesa keyboard, keypad, mouse, trackball, trackpad, and/or cursor directionkeys for communicating information and commands to processor 1102.

System 1100 also includes network interface 1112 coupled to theprocessor 1102. Network interface 1112 allows system 1100 to communicatewith network 1114, to which one or more other computer systems areconnected. Network interface 1112 includes wireless network interfacessuch as BLUETOOTH, WIFI, WIMAX, GPRS, or WCDMA; or wired networkinterface such as ETHERNET, USB, or IEEE-1394. In some embodiments,method 1000 is implemented in two or more systems 1100, and informationsuch as layout design, and user interface are exchanged betweendifferent systems 1100 by network 1114.

System 1100 is configured to receive information related to a layoutdesign through I/O interface 1110 or network interface 1112. Theinformation is transferred to processor 1102 by bus 1108 to determine alayout design for producing IC 200 or 400. The layout design is thenstored in computer readable medium 1104 as layout design 1116. System1100 is configured to receive information related to a user interfacethrough I/O interface 1110 or network interface 1112. The information isstored in computer readable medium 1104 as user interface 1118.

In some embodiments, method 1000 is implemented as a standalone softwareapplication for execution by a processor. In some embodiments, method1000 is implemented as a software application that is a part of anadditional software application. In some embodiments, method 1000 isimplemented as a plug-in to a software application. In some embodiments,method 1000 is implemented as a software application that is a portionof an EDA tool. In some embodiments, method 1000 is implemented as asoftware application that is used by an EDA tool. In some embodiments,the EDA tool is used to generate a layout of the integrated circuitdevice. In some embodiments, the layout is stored on a non-transitorycomputer readable medium. In some embodiments, the layout is generatedusing a tool such as VIRTUOSO® available from CADENCE DESIGN SYSTEMS,Inc., or another suitable layout generating tool. In some embodiments,the layout is generated based on a netlist which is created based on theschematic design. In some embodiments, method 1000 is implemented by amanufacturing device to manufacture an integrated circuit using a set ofmasks manufactured based on one or more layout designs generated bysystem 1100. System 1100 of FIG. 11 generates layout designs of anintegrated circuit that are smaller than other approaches.

System 1100 of FIG. 11 generates layout designs of integrated circuitstructure that occupy less area and have consume less power than otherapproaches. In some embodiments system 1100 is a MBFF banking/de-bankingengine.

FIG. 12 is a block diagram of an integrated circuit (IC) manufacturingsystem 1000, and an IC manufacturing flow associated therewith, inaccordance with at least one embodiments of the present disclosure.

In FIG. 12, IC manufacturing system 1200 includes entities, such as adesign house 1220, a mask house 1240, and an IC manufacturer/fabricator(“fab”) 1240, that interact with one another in the design, development,and manufacturing cycles and/or services related to manufacturing an ICdevice 1260. The entities in system 1200 are connected by acommunications network. In some embodiments, the communications networkis a single network. In some embodiments, the communications network isa variety of different networks, such as an intranet and the Internet.The communications network includes wired and/or wireless communicationchannels. Each entity interacts with one or more of the other entitiesand provides services to and/or receives services from one or more ofthe other entities. In some embodiments, two or more of design house1220, mask house 1240, and IC fab 1240 is owned by a single largercompany. In some embodiments, two or more of design house 1220, maskhouse 1240, and IC fab 1240 coexist in a common facility and use commonresources.

Design house (or design team) 1220 generates an IC design layout 1222.IC design layout 1222 includes various geometrical patterns designed foran IC device 1260. The geometrical patterns correspond to patterns ofmetal, oxide, or semiconductor layers that make up the variouscomponents of IC device 1260 to be fabricated. The various layerscombine to form various IC features. For example, a portion of IC designlayout 1222 includes various IC features, such as an active region, gateelectrode, source electrode and drain electrode, metal lines or vias ofan interlayer interconnection, and openings for bonding pads, to beformed in a semiconductor substrate (such as a silicon wafer) andvarious material layers positioned on the semiconductor substrate.Design house 1220 implements a proper design procedure to form IC designlayout 1222. The design procedure includes one or more of logic design,physical design or place and route. IC design layout 1222 is presentedin one or more data files having information of the geometricalpatterns. For example, IC design layout 1222 can be expressed in a GDSIIfile format or DFII file format.

Mask house 1240 includes data preparation 1252 and mask fabrication1244. Mask house 1240 uses IC design layout 1222 to manufacture one ormore masks to be used for fabricating the various layers of IC device1260 according to IC design layout 1222. Mask house 1240 performs maskdata preparation 1252, where IC design layout 1222 is translated into arepresentative data file (“RDF”). Mask data preparation 1252 providesthe RDF to mask fabrication 1244. Mask fabrication 1244 includes a maskwriter. A mask writer converts the RDF to an image on a substrate, suchas a mask (reticle) or a semiconductor wafer. The design layout ismanipulated by mask data preparation 1252 to comply with particularcharacteristics of the mask writer and/or requirements of IC fab 1240.In FIG. 12, mask data preparation 1252 and mask fabrication 1244 areillustrated as separate elements. In some embodiments, mask datapreparation 1252 and mask fabrication 1244 can be collectively referredto as mask data preparation.

In some embodiments, mask data preparation 1252 includes opticalproximity correction (OPC) which uses lithography enhancement techniquesto compensate for image errors, such as those that can arise fromdiffraction, interference, other process effects and the like. OPCadjusts IC design layout 1222. In some embodiments, mask datapreparation 1252 includes further resolution enhancement techniques(RET), such as off-axis illumination, sub-resolution assist features,phase-shifting masks, other suitable techniques, and the like orcombinations thereof. In some embodiments, inverse lithographytechnology (ILT) is also used, which treats OPC as an inverse imagingproblem.

In some embodiments, mask data preparation 1252 includes a mask rulechecker (MRC) that checks the IC design layout that has undergoneprocesses in OPC with a set of mask creation rules which contain certaingeometric and/or connectivity restrictions to ensure sufficient margins,to account for variability in semiconductor manufacturing processes, andthe like. In some embodiments, the MRC modifies the IC design layout tocompensate for limitations during mask fabrication 1244, which may undopart of the modifications performed by OPC in order to meet maskcreation rules.

In some embodiments, mask data preparation 1252 includes lithographyprocess checking (LPC) that simulates processing that will beimplemented by IC fab 1240 to fabricate IC device 1260. LPC simulatesthis processing based on IC design layout 1222 to create a simulatedmanufactured device, such as IC device 1260. The processing parametersin LPC simulation can include parameters associated with variousprocesses of the IC manufacturing cycle, parameters associated withtools used for manufacturing the IC, and/or other aspects of themanufacturing process. LPC takes into account various factors, such asaerial image contrast, depth of focus (“DOF”), mask error enhancementfactor (“MEEF”), other suitable factors, and the like or combinationsthereof. In some embodiments, after a simulated manufactured device hasbeen created by LPC, if the simulated device is not close enough inshape to satisfy design rules, OPC and/or MRC are be repeated to furtherrefine IC design layout 1222.

It should be understood that the above description of mask datapreparation 1252 has been simplified for the purposes of clarity. Insome embodiments, data preparation 1252 includes additional featuressuch as a logic operation (LOP) to modify the IC design layout accordingto manufacturing rules. Additionally, the processes applied to IC designlayout 1222 during data preparation 1252 may be executed in a variety ofdifferent orders.

After mask data preparation 1252 and during mask fabrication 1244, amask or a group of masks are fabricated based on the modified IC designlayout. In some embodiments, an electron-beam (e-beam) or a mechanism ofmultiple e-beams is used to form a pattern on a mask (photomask orreticle) based on the modified IC design layout. The mask can be formedin various technologies. In some embodiments, the mask is formed usingbinary technology. In some embodiments, a mask pattern includes opaqueregions and transparent regions. A radiation beam, such as anultraviolet (UV) beam, used to expose the image sensitive material layer(e.g., photoresist) which has been coated on a wafer, is blocked by theopaque region and transmits through the transparent regions. In oneexample, a binary mask includes a transparent substrate (e.g., fusedquartz) and an opaque material (e.g., chromium) coated in the opaqueregions of the mask. In another example, the mask is formed using aphase shift technology. In the phase shift mask (PSM), various featuresin the pattern formed on the mask are configured to have proper phasedifference to enhance the resolution and imaging quality. In variousexamples, the phase shift mask can be attenuated PSM or alternating PSM.The mask(s) generated by mask fabrication 944 is used in a variety ofprocesses. For example, such a mask(s) is used in an ion implantationprocess to form various doped regions in the semiconductor wafer, in anetching process to form various etching regions in the semiconductorwafer, and/or in other suitable processes.

IC fab 1240 is an IC fabrication business that includes one or moremanufacturing facilities for the fabrication of a variety of differentIC products. In some embodiments, IC Fab 1240 is a semiconductorfoundry. For example, there may be a manufacturing facility for thefront end fabrication of a plurality of IC products (front-end-of-line(FEOL) fabrication), while a second manufacturing facility may providethe back end fabrication for the interconnection and packaging of the ICproducts (back-end-of-line (BEOL) fabrication), and a thirdmanufacturing facility may provide other services for the foundrybusiness.

IC fab 1240 uses the mask (or masks) fabricated by mask house 1240 tofabricate IC device 1260. Thus, IC fab 1240 at least indirectly uses ICdesign layout 1222 to fabricate IC device 1260. In some embodiments, asemiconductor wafer 1252 is fabricated by IC fab 1240 using the mask (ormasks) to form IC device 1260. Semiconductor wafer 1252 includes asilicon substrate or other proper substrate having material layersformed thereon. Semiconductor wafer further includes one or more ofvarious doped regions, dielectric features, multilevel interconnects,and the like (formed at subsequent manufacturing steps).

Details regarding an integrated circuit (IC) manufacturing system (e.g.,system 1000 of FIG. 10), and an IC manufacturing flow associatedtherewith are found, e.g., in U.S. Pat. No. 9,256,709, granted Feb. 9,2016, U.S. Pre-Grant Publication No. 20150278429, published Oct. 1,2015, U.S. Pre-Grant Publication No. 20140040838, published Feb. 6,2014, and U.S. Pat. No. 7,260,442, granted Aug. 21, 2007, the entiretiesof each of which are hereby incorporated by reference.

An aspect of this description is related to an integrated circuitstructure that includes a substrate having a front side and a back side,the back side being an opposite side of the substrate from the frontside. A first power rail extends in a first direction, being embedded inthe front side of the substrate and configured to provide a first supplyvoltage. A second power rail is configured to provide a second supplyvoltage different from the first supply voltage, the second power railextending in the first direction, being embedded in the front side ofthe substrate and being separated from the first power rail in a seconddirection different from the first direction. A first device ispositioned between the first power rail and the second power rail andlocated on the front side of the substrate. A first via structureextends to the back side of the substrate and is electrically coupled tothe second power rail.

Another aspect of this description is related to a method of forming anintegrated circuit (IC) that includes generating, by a processor, a celllayout design of the integrated circuit. The generating of the celllayout design includes generating a first power rail layout patternextending in a first direction and corresponding to a first power railin a front side of a substrate and configured to provide a first supplyvoltage, and generating a second power rail layout pattern extending inthe first direction and separated from the first power rail layoutpattern in a second direction different from the first direction, thesecond power rail layout pattern corresponding to a second power rail inthe front side of the substrate and configured to provide a secondsupply voltage different from the first supply voltage. Also, the methodincludes generating a set of first device layout patterns positionedbetween the first power rail layout pattern and the second power raillayout pattern and corresponding to a set of devices. Moreover, themethod includes generating a first via layout pattern corresponding to afirst via structure, the first via structure extending to a backside ofthe substrate and electrically coupled to the second power rail.Furthermore, the method includes manufacturing the integrated circuitbased on the cell layout design.

A further aspect of this description includes an integrated circuit thatincludes a substrate having a front side and a back side, the back sidebeing an opposite side of the substrate from the front side. A hybridpower rail structure at least partially embedded in the front side ofthe substrate. The hybrid power rail includes a first buried power railconfigured to provide a first supply voltage, and a second buried powerrail coupled to the first buried power rail and configured to provide asecond supply voltage. The integrated circuit includes a via structureelectrically coupled to the second buried power rail and configured toprovide backside power.

The foregoing outlines features of several embodiments so that thoseskilled in the art may better understand the aspects of the presentdisclosure. Those skilled in the art should appreciate that they mayreadily use the present disclosure as a basis for designing or modifyingother processes and structures for carrying out the same purposes and/orachieving the same advantages of the embodiments introduced herein.Those skilled in the art should also realize that such equivalentconstructions do not depart from the spirit and scope of the presentdisclosure, and that they may make various changes, substitutions, andalterations herein without departing from the spirit and scope of thepresent disclosure.

What is claimed is:
 1. An integrated circuit comprising: a substratehaving a front side and a back side, the back side being an oppositeside of the substrate from the front side; a first power rail extendingin a first direction, being embedded in the front side of the substrateand configured to provide a first supply voltage, wherein the firstpower rail has a first height between the front side and the back side;a second power rail configured to provide a second supply voltagedifferent from the first supply voltage, the second power rail extendingin the first direction, being embedded in the front side of thesubstrate and being separated from the first power rail in a seconddirection different from the first direction, wherein the second powerrail has a second height between the front side and the back side, thesecond height being greater than the first height; a first devicepositioned between the first power rail and the second power rail, andlocated on the front side of the substrate; and a first via structureextending to the back side of the substrate and electrically coupled tothe second power rail.
 2. The integrated circuit of claim 1, wherein thefirst power rail comprises a metal layer positioned on the first device.3. The integrated circuit of claim 1, wherein the second power rail is aburied power rail.
 4. The integrated circuit of claim 1, wherein thefirst power rail is electrically coupled to a conductive device.
 5. Theintegrated circuit of claim 4, wherein the conductive device extends inthe first direction in a layer above the first device, the first powerrail and the second power rail.
 6. The integrated circuit of claim 4,wherein the first power rail is electrically coupled to the conductivedevice through a second via structure.
 7. The integrated circuit ofclaim 1, wherein the first supply voltage and the second supply voltageare of different values.
 8. The integrated circuit of claim 1, whereinthe first via structure is a through silicon via.
 9. The integratedcircuit of claim 1, wherein the first device comprises passive devicesand active devices.
 10. An integrated circuit comprising: a substratehaving a front side and a back side, the back side being an oppositeside of the substrate from the front side; a hybrid power rail structureat least partially embedded in the front side of the substratecomprising: a first buried power rail extending in a first direction andconfigured to provide a first supply voltage and having a first heightthat extends between the front side and the back side of the substrate;a second buried power rail extending in the first direction andconfigured to provide a second supply voltage, the second buried powerrail being separated from the first buried power rail in a seconddirection different from the first direction and having a second heightgreater than the first height; and a via structure electrically coupledto the second buried power rail and configured to provide backsidepower.
 11. The integrated circuit of claim 10, wherein the first buriedpower rail comprises a bottom protective layer.
 12. The integratedcircuit of claim 10, wherein the via structure is a through silicon via.13. An integrated circuit comprising: a substrate having a firstdirection extending from a back side of the substrate to a front side ofthe substrate; a first power rail embedded in the front side of thesubstrate positioned at a first height along the first direction andextending in a second direction perpendicular to the first direction; asecond power rail embedded in the front side of the substrate and beingseparated from the first power rail in a third direction different fromthe first and second direction and positioned at a second height alongthe first direction and extending in the second direction, the secondheight being closer to the back side of the substrate than the firstheight; a device structure positioned between the first power rail andthe second power rail; and a first via structure extending from the backside of the substrate to the second power rail.
 14. The integratedcircuit of claim 13, wherein the device structure comprises a pluralityof conductive structures extending in the first direction and positionedat a first level.
 15. The integrated circuit of claim 14, wherein theplurality of conductive structures comprises a total of four conductivestructures positioned between the first power rail and the second powerrail.
 16. The integrated circuit of claim 13, further comprising: athird power rail positioned at the first height and parallel to thefirst power rail; and a fourth power rail positioned at the secondheight and parallel to the second power rail, wherein the first andthird power rails are configured to provide a first supply voltage, andthe second and fourth power rails are configured to provide a secondsupply voltage different from the first supply voltage.
 17. Theintegrated circuit of claim 16, further comprising: a second viastructure extending from the back side of the substrate to the secondpower rail; a third via structure extending from the back side of thesubstrate to the fourth power rail; and a fourth via structure extendingfrom the back side of the substrate to the fourth power rail.
 18. Theintegrated circuit of claim 13, wherein the device structure comprises aplurality of gate structures extending in a third directionperpendicular to each of the first and second directions, the pluralityof gate structures being positioned at a third height between the firstand second heights.
 19. The integrated circuit of claim 18, wherein thefirst power rail overlies the plurality of gate structures, and theplurality of gate structures overlies the second power rail.
 20. Theintegrated circuit of claim 13, wherein the second height along thefirst direction is greater than the first height along the firstdirection.